1. Field of the Invention
This invention relates generally to network interfaces transferring data between a host processing device and a network connection. In particular, the present invention relates to memory utilization in a network interface controller transferring data between a network connection and a host interface or bus.
2. Description of the Related Art
A network interface controller (NIC) generally acts as the communications intermediary between a network and a host processing system. In a host processing system such as a server, there may be a large amount of data storage and communications functionality and the performance of the host processing system may be adversely affected by the demands of the NIC to access processors and other resources during data transfer operations.
The Virtual Interface (VI) Architecture, Version 1.0, published Dec. 16, 1997 was developed to enable NICs to carry out efficient, low overhead, data transfers without making large demands on the processor(s) of the host processing system. It decouples the processor(s) from the I/O subsystem and transfers data directly to and from host memory using a plurality of send queues which transmit request packets and receive response packets and a plurality of receive queues which receive request packets and transmit response packets. While a VI NIC addresses the problems of reliability, performance and complexity in the host processing system, the management of the send and receives queues increases the complexity within the VI NIC. Each send queue and each receive queue are able to both transmit and receive data. A context memory can be used for storing the state information of each send queue and each receive queue. Each data packet received or transmitted requires reading and modifying the context of the appropriate send queue or receive queue. Furthermore the data packets must be tracked in the NIC. For a send queue, a descriptor in the main memory indicates the type of packet (send, write, read) and the location where the data is to be written or read. This can be done by storing the sequence number and packet type for each of the packets. But, this has the disadvantage of requiring a larger and more complex context memory and method of accessing the data in the context memory.
FIG. 1 is a block diagram illustrating a typical arrangement of the context memory and the transmit and receive engines for tracking data packets in a NIC. Receiver 102 passes data received from the network to receive engine 104. Transmit engine 103 provides data to be transmitted over the network to transmitter 101. Transmitter 101 and receiver 102 connect only to transmit engine 103 and receive engine 104, respectively. Receive engine 104 receives: 1) request packets sent by the send queue of another NIC to receive queues in the NIC; and 2) response packets from the receive queue of another NIC responding to request packets sent from send queues in the NIC through receiver 102. It handles the packets according to context data in send queue context 106 and receive queue context 105 and provides the data from the packets to the host via host interface 107. Transmit engine 103 transmits: 1) request packets from send queues in the NIC to the receive queues in another NIC; and 2) response packets from a receive queue in the NIC responding to request packets sent by the send queues of another NIC through transmitter 101. Transmit engine 103 obtains data from the host via host interface 107 and provides it to transmitter 101 to be transmitted according to the descriptors and the context data in send queue context 106 and receive queue context 105. As shown, transmit engine 103 and receive engine 104 both access the send queue context 106 and receive queue context 105 to obtain the context of the send queues and receive queues.
An example of a NIC with separate receive channel and transmit channel DMA engines and a single memory shared by the engines appears at page 76 of the Aug. 24, 1998 issue of Electronic Engineering Times. The memory access controller apparently arbitrates accesses to the shared memory requested by the separate transmit and receive engines. This forces one engine to wait if both engines attempt accesses simultaneous or near-simultaneous accesses. Also, simultaneous or near-simultaneous accesses may attempt to modify the same send or receive queue context. Modification procedures in the memory access controller must take them into account so that they do not work on the same send or receive queue context at the same time. A dual-port memory could be used as in FIG. 1, but that would double the number of necessary connections to the memory and still not resolve the problem of simultaneous accesses or simultaneously accessing the same send queue or receive queue. Furthermore, creating a dual-port memory is undesirable in any event because it makes the memory larger, more complex, and slower.